Error-Transparent Quantum Gates for Small Logical Qubit Architectures

Physical Review Letters
Eliot Kapit

Abstract

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both....Continue Reading

References

Sep 6, 2000·Physical Review Letters·A BeigeP L Knight
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Dec 13, 2006·Physical Review Letters·F YoshiharaJ S Tsai
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Apr 23, 2016·Physical Review Letters·Victor V AlbertLiang Jiang
Sep 28, 2017·Physical Review Letters·Joachim CohenMazyar Mirrahimi
Oct 28, 2017·Physical Review Letters·Yao LuDavid I Schuster

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Citations

Sep 26, 2020·Physical Review Letters·Wen-Long MaLiang Jiang
Jul 22, 2018·Science·S RosenblumR J Schoelkopf

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