Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid

Philosophical Transactions. Series A, Mathematical, Physical, and Engineering Sciences
James Alfred WalkerAndy M Tyrrell

Abstract

The project Meeting the Design Challenges of nano-CMOS Electronics (http://www.nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function ex...Continue Reading

References

Dec 8, 2005·Food Additives and Contaminants·J Fink-Gremmels

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Citations

Dec 14, 2011·International Journal of Surgery·Chih-Hao ChenTzu-Ti Hung
Jul 21, 2010·Philosophical Transactions. Series A, Mathematical, Physical, and Engineering Sciences·Mark BirkinRichard Sinnott

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