DOI: 12, 2021Proceedings Paper

Projeto e Avaliação de uma Arquitetura do Algoritmo de Clusterização K-means em VHDL e FPGA

Matheus Alcântara SouzaHenrique Cota de Freitas


O crescimento constante no volume de bases de dados em variadas áreas de pesquisa tem demandado arquiteturas de computadores mais eficazes para a utilização de algoritmos de mineração de dados, de maneira a realizar análises eficientes dessas bases. Mais desempenho é necessário, e arquiteturas mais poderosas tendem a consumir mais energia, acrescentando desafios para os projetos de hardware de processadores. Dessa forma, o projeto de novas arquiteturas com eficiência energética se faz necessário. Este trabalho propõe o projeto e avaliação de uma arquitetura em VHDL e FPGA para o algoritmo de clusterização K-means, visando alto desempenho em arquiteturas heterogêneas. Os resultados mostram que a implementação proposta apresenta uma redução de 91% em relação número de ciclos executados por um processador Intel Xeon E5-2620, consumindo até 95% menos energia.

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