Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Sensors
Alberto SciontiAntoni Portero

Abstract

The rapid evolution of Cloud-based services and the growing interest in deep learning (DL)-based applications is putting increasing pressure on hyperscalers and general purpose hardware designers to provide more efficient and scalable systems. Cloud-based infrastructures must consist of more energy efficient components. The evolution must take place from the core of the infrastructure (i.e., data centers (DCs)) to the edges (Edge computing) to adequately support new/future applications. Adaptability/elasticity is one of the features required to increase the performance-to-power ratios. Hardware-based mechanisms have been proposed to support system reconfiguration mostly at the processing elements level, while fewer studies have been carried out regarding scalable, modular interconnected sub-systems. In this paper, we propose a scalable Software Defined Network-on-Chip (SDNoC)-based architecture. Our solution can easily be adapted to support devices ranging from low-power computing nodes placed at the edge of the Cloud to high-performance many-core processors in the Cloud DCs, by leveraging on a modular design approach. The proposed design merges the benefits of hierarchical network-on-chip (NoC) topologies (via fusing the ring ...Continue Reading

References

May 29, 2015·Nature·Yann LeCunGeoffrey Hinton
Mar 26, 2018·Entropy·Jesús Antonio Puente FernándezTai-Hoon Kim

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Citations

Mar 7, 2021·Micromachines·Jose Ricardo Gomez-RodriguezRamon Parra-Michel
Sep 26, 2019··Marcelo RuaroFernando G. Moraes

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Methods Mentioned

BETA
chip
ISA
chips

Software Mentioned

OS
Codelet
Goroutines
Xilinx
TensorFlow
PyTorch
Go
Apache MLlib
Catapult
Go P4

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